1. Field of the Invention
The present invention relates to a method of fabricating memory. More particularly, the present invention relates to a method of fabricating non-volatile memory.
2. Description of the Related Art
Among the non-volatile memory products, electrically erasable and programmable read-only-memory (EEPROM) is a device that allows multiple data entry, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, the memory device has been broadly applied in personal computer and electronic equipment.
In U.S. Pat. No. 4,939,690, a flash memory structure having a floating gate and a control gate fabricated using doped polysilicon is provided. To prevent the mis-judgement errors due to the over-erasure of the flash memory in the erasing operation, additional select gates are formed on the sidewalls of the control gates and the floating gates and over the substrate to form the so-called split-gate structure.
Moreover, a charge storage layer sometimes replaces the polysilicon floating gates in the conventional design technique. The charge storage layer is fabricated using silicon nitride, for example. In general, the silicon nitride charge storage layer is sandwiched between a top and a bottom silicon oxide layer to form an oxide/nitride/oxide (ONO) composite layer. A device having this type of structure is often called a silicon/oxide/nitride/oxide/silicon (SONOS) device. In U.S. Pat. No. 5,930,631, a SONOS device having a split-gate structure has been disclosed.
However, the aforementioned SONOS device with split-gate structure needs more memory space because a larger split-gate area is required to accommodate the split gate structure. Therefore, the SONOS device has memory cells with a size much greater than that of the stack gate EEPROM. In other words, it is difficult to increase the level of integration of the SONOS device with split-gate cell structures any further.